ECE – VLSI

CODEPROJECT NAMEYEARDOWNLOAD ABSTRACTS
VL_01Design of Low Power TPG Using LP-LFSR2018DOWNLOAD
VL_02Multi-operand redundant adders on FPGAs2018DOWNLOAD
VL_03ASIC Implementation of DDR SDRAM Memory Controller2018DOWNLOAD
VL_04Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip2018DOWNLOAD
VL_05Design a DSP Operations using Vedic Mathematics2018DOWNLOAD
VL_06Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA2018DOWNLOAD
VL_07VLSI implementation of Fast Addition using Quaternary Signed Digit Number System2018DOWNLOAD
VL_08A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler2018DOWNLOAD
VL_09A Decimal / Binary Multi-operand Adder using a Fast Binary to Decimal Converter2018DOWNLOAD
VL_10A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT2018DOWNLOAD
VL_11A Novel Parallel Multiplier for 2’s Complement Numbers Using Booth’s Recoding Algorithm2018DOWNLOAD
VL_12Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic2018DOWNLOAD
VL_13An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator2018DOWNLOAD
VL_14Area-Delay Efficient Binary Adders in QCA2018DOWNLOAD
VL_15Area–Delay–Power Efficient Carry-Select Adder2018DOWNLOAD
VL_16FPGA BASED PARTIAL RECONFIGURABLE FIR FILTER DESIGN2018DOWNLOAD
VL_17Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications2018DOWNLOAD
VL_18High Speed Convolution and De convolution Algorithm (Based on Ancient Indian Vedic Mathematics)2018DOWNLOAD
VL_19High Throughput Architecture for the Advanced Encryption Standard Algorithm2018DOWNLOAD
VL_20Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions2018DOWNLOAD
VL_21Low-Power Programmable PRPG With Test Compression Capabilities2018DOWNLOAD
VL_22Novel Shared Multiplier Scheduling Scheme for Area-Efficient FFT/IFFT Processors2018DOWNLOAD
VL_23Obfuscating DSP Circuits via High-Level Transformations2018DOWNLOAD
VL_24On-Chip Code word Generation to Cope With Crosstalk2018DOWNLOAD
VL_25Partially Parallel Encoder Architecture for Long Polar Codes2018DOWNLOAD
VL_26Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations2018DOWNLOAD
VL_27Simplified Trellis Min–Max Decoder Architecture for Non binary Low-Density Parity-Check Codes2018DOWNLOAD
VL_28A Low-Power Hybrid RO PUF With Improved Thermal Stability for Lightweight Applications2018DOWNLOAD
VL_29A Novel Area-Efficient VLSI Architecture for Recursion Computation in LTE Turbo Decoders2018DOWNLOAD
VL_30A Novel Realization of Reversible LFSR for its Application in Cryptography2018DOWNLOAD
VL_31An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm forReconfigurable FIR Filter Synthesis2018DOWNLOAD
VL_32An Enhanced Architecture for High Performance BIST TPG2018DOWNLOAD
VL_33Design & Analysis of 16 bit RISC Processor Using low Power Pipelining2018DOWNLOAD
VL_34Design and FPGA Implementation of Optimized 32- Bit Vedic Multiplier and Square Architectures2018DOWNLOAD
VL_35Design and Implementation of Dynamic Key Based Stream Cipher for Cryptographic Processor2018DOWNLOAD
VL_36DESIGN AND TESTING OF COMBINATIONAL LOGIC CIRCUITS USING BUILT IN SELF TEST SCHEME FOR FPGAs2018DOWNLOAD
VL_37Design of Carry Select Adder for Low-Power and High Speed VLSI Applications2018DOWNLOAD
VL_38Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology2018DOWNLOAD
VL_39Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks2018DOWNLOAD
VL_40FPGA Implementation of Dual Key Based AES Encryption with Key Based S-Box Generation2018DOWNLOAD
VL_41FPGA Realisation of Multiplier less FIR Filter Architectures2018DOWNLOAD
VL_42Implementation of A High Speed Multiplier for High-Performance and Low Power Applications2018DOWNLOAD
VL_43Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding2018DOWNLOAD
VL_44Low-Power and Area-Efficient Shift Register Using Pulsed Latches2018DOWNLOAD
VL_45Novel Vedic Mathematics Based ALU Using Application Specific Reversibility2018DOWNLOAD
VL_46On the Analysis of Reversible Booth’s Multiplier2018DOWNLOAD
VL_47On-Chip Comparison based Secure Output Response Compactor for Scan-based Attack Resistance2018DOWNLOAD
VL_48Reliable and Error Detection Architectures of Pomaranch for False-Alarm-Sensitive Cryptographic Applications2018DOWNLOAD
VL_49Variable Latency Speculative Han-Carlson Adder2018DOWNLOAD
VL_50VLSI Implementation of an efficient Fused Add Multiply Unit using Constant-time addition2018DOWNLOAD
VL_51IMPROVED MATRIX MULTIPLICATION USING MUX FOR HIGH SPEED DSP APPLICATIONS2018DOWNLOAD
VL_52Design and Simulation of ZIGBEE Transmitter Using Verilog2018DOWNLOAD
VL_53High Speed and Low Power implementation of 3-Weight Pattern Generation Based on Accumulator2018DOWNLOAD
VL_5432 Bit×32 Bit Multi precision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler2018DOWNLOAD
VL_55A parallel radix-sort-based VLSI architecture for finding the first W maximum/minimum values2018DOWNLOAD
VL_56Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay2018DOWNLOAD
VL_57Design and Analysis of Approximate Compressors for Multiplication2018DOWNLOAD
VL_58An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability2018DOWNLOAD
VL_59Low-Complexity Tree Architecture for Finding the First Two Minima2018DOWNLOAD
VL_60Recursive Approach to the Design of a Parallel Self-Timed Adder2018DOWNLOAD
VL_61A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications2018DOWNLOAD
VL_62Digital Multiplier less Realization of Two-Coupled Biological Hind marsh–Rose Neuron Model2018DOWNLOAD
VL_63High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels2018DOWNLOAD